1. Field of the Invention
The present invention relates to a memory system including a nonvolatile semiconductor memory.
2. Description of the Related Art
In recent years, nonvolatile semiconductor storage devices such as a flash memory for storing information according to an amount of accumulated charges are widely known. Recently, a capacity of a NAND flash memory is increased. A personal computer incorporating the NAND flash memory as a secondary storage device is put to practical use. In such a NAND flash memory has a characteristic that deterioration of memory cells worsens according to an increase in the number of times of erasing of a block performed prior to data writing. Therefore, processing called wear leveling for equally distributing data storage places in the memory cells is performed to generally equalize the numbers of times of erasing of all the memory cells.
In the NAND flash memory, because of the characteristics of the memory cells, data recording is performed by effectively making use of all areas of a storage area. Therefore, processing for rewriting even data once written in the memory cells in a new storage area is frequently performed because of a relation with data written after the data or other data written in the memory cells.
Further, in the NAND flash memory, because charges are discharged according to the elapse of time, an error occurs during readout of information when charges are discharged exceeding a threshold. In particular, in a multi-value type storage element that that stores 2-bit or larger information in one memory cell, in general, since an interval of a threshold is narrow, it is highly likely that an error occurs.
In such a technical background, as a technology for correcting an error of data stored in a nonvolatile semiconductor memory, for example, Japanese Patent Application Laid-Open No. 11-154394 (hereinafter abbreviated as Patent Document 1) discloses a technology for grouping, to secure reliability of stored data, a fixed number of storage elements, giving error correction codes to the storage elements, and correcting an error of information according to the error correction codes.
However, in the technology disclosed in Patent Document 1, an error always occurs during readout in a storage element in which a charge amount exceeds a threshold because of discharge. The same error correction processing has to be performed every time data is read out. Therefore, when the technology is applied to the NAND flash memory in which stored data is frequently moved, processing time of error correction processing increases and a storage area has to be secured according to the error correction processing. As a result, efficiency of write processing cannot be realized.
Error correction for all data is not always possible. The technology disclosed in Patent Document 1 does not take into account this point. When data for which error correction is impossible is present, this is equivalent to a state in which the data is broken. When processing same as that for normal data without an error is continued for such data with an error, the data with the error is directly copied. Thereafter, the error cannot be detected in error detection processing. As a result, the data with the error is recognized as data without an error and reliability of stored data falls.